This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.
As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or "front end", controllers and "back end" disk controllers. The interface operates the controllers in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled "System and Method for Disk Mapping and Data Retrieval", inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. patent, the interface may also include, in addition to the CPU controllers and disk controllers, addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set of the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set of the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail.
In one system, the communication to the controllers and the cache memories is through a pair of bi-directional lines. Typically one bi-directional line is for data and the other bi-directional line is for control signals. As noted above, each controller is connected to only one of the buses and, therefore, only one pair of bi-directional lines are electrically connected to the controllers; however, because each one of the cache memories is connected to both buses, each cache memory has two pairs of bidirectional lines.
One such data storage system is an asynchronous system. In such system, when a controller wishes to read data from an addressed memory, the addressed memory places the data and a clock pulse on the bus. The data and the clock travel along the bus to the controller, the controller receives the data and clocks the data into the controller using the clock placed on the bus by the addressed memory. When the controller wishes to have data written into an addressed memory, the controller places the data on the bus and the addressed memory must strobe the data on the bus into itself. However, because the system is asynchronous, the addressed memory may not be ready to accept the data on the bus. Therefore, when addressed by the controller, the memory places a clock on the bus, the clock runs to the controller, the controller detects the clock sent by the addressed memory and places the data on the bus. The data runs back to the addressed memory, and then, after a predetermined round-trip time, the addressed memory clocks in the data. While the round-trip is a function of the distance between the controller and the addressed memory, system is designed with the a predetermined round-trip time sufficient to account for the maximum expected roundtrip time. Thus, in those cases where the controller and addressed memory pair are relative close together, time is lost in waiting for the maximum predetermined round-trip time before the addressed memory writes in the data on the bus.
Another asynchronous data storage system is described in co-pending patent application Ser. No. 08/701,862, filed Aug. 23, 1996, inventors John K. Walton, et al. entitled TIMING PROTOCOL FOR A DATA STORAGE SYSTEM, assigned to the same assignee as the present invention, the entire subject matter thereof being incorporated herein by reference. Such system includes a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus having: an bus-select/address/command portion; and a bus-grant/data/clock-pulse portion. Each one of the controllers is adapted to assert on the bus-select/command/address portion of the bus a command during a controller initiated bus select assert interval. The command includes: (i) a read operation request or a write operation request; and (ii) an address to address one of the addressable memories selected by the controller to respond to the read operation request or write operation request. In response to the command, the memories decode the address. The addressed memory, having a common random access memory (RAM) shared by the pair of buses, proceeds with any necessary bus arbitration. Once this decode and internal memory bus arbitration is performed, the RAM in the memory is addressed in a row address select/column address select (RAS/CAS) manner. After this decode/arbitration/RAS/CAS interval (i.e., latent system delay) is completed, the memory asserts the bus-grant/data/clock pulse portion of the bus and the controller, in response to the memory assert, de-asserts the bus select to thereby enable another controller to assert the bus. In order to provide some suppression of the address decode/bus arbitration/RAS/CAS latent system delay), a pre-fetch operation is provided. More particularly, each one of the memories includes the RAM, which is accessible to both buses; an internal clock; a pair of buffer memories, each one coupled to a corresponding one of the buses; and a pair of control logic networks each one coupled to a corresponding one of the pair of buses. Each control logic network is configured to enable data on the bus to commence being written into the buffer memory in response to initiation of the bus select interval and to enable the data written into the buffer memory to be read therefrom and transferred to the bus during the data transfer, bus grant interval. The data is written into, and read from, the buffer memory in response to clock pulses produced by the internal clock. With this arrangement, data may be transferred between a bus and the RAM of one addressed memory while data is being transferred from between a RAM of a second addressed memory and the buffer memory thereof for subsequent transfer to the bus. This pre-fetch operation reduces the latent system delay described above.